1. Field of the Invention
The present invention relates to an improved pulse width modulation technique. The invention is particularly advantageous when applied in a method or system for the efficient generation of a switched power supply. The invention finds particular advantageous application in mobile communication handsets, although the invention is not limited to such an application.
2. Description of the Related Art
It is known in the art that efficient power supply generation requires some form of switching means rather than a linear regulator providing a constant voltage. Switched mode power supplies are well-known in the art. Switched mode power supplies have, however, been typically used for static or slowly varying DC voltages. In such applications, the main consideration for the transient response is to respond to rapid changes in the load current rather than rapid changes in output voltage.
With recent advances in radio communications, and more particularly in mobile telecommunications, efficient operation of transmitters is required for applications in which there are rapidly varying output amplitudes. It is known in the art to address the need for such efficient operation using two techniques. A first technique is known as envelope tracking (ET), and a second technique is known as envelope elimination and restoration (EER). These techniques have required the development of a power supply requiring the efficient provision of a wide output range where the output voltage is expected to show rapid and large signal variations, in addition to variations in the load current.
A typical switch mode implementation is to include a highly non-linear switching block inside a feedback loop, such that the output is effectively linearised by the feedback for signals at a frequency much less than the switching frequency. There are three commonly used methodologies for switch mode implementations: i) Pulse Width Modulation (PWM); ii) Hysteretic (also known as Bang Bang); and iii) Delta Sigma.
A typical PWM technique comprises providing a ramp that is initiated at the start of each clock cycle. At the start of each clock cycle the switch output is set to be “1”. When the ramp crosses the signal, the signal output switches to “0”. This means that over a single cycle, the average of the output signal is equal to the control inputs, resulting in quasi-linear operation that provides inherently accurate tracking. Conventional PWM algorithms begin to fail when there is a significant change of signal level within one ramp cycle. When the signal changes rapidly, the quasi-linearity is lost and the function becomes a unit level quantiser with delay. This increased delay can result in large signal limit cycle oscillations occurring with wide bandwidth loops.
One problem of prior art techniques is to provide good switching accuracy at large bandwidths. One solution is to increase the switching rate. This means that switcher states are updated at a faster rate and hence are more able to follow fast changing signals.
However when the switched mode supply is implemented using CMOS technology, the switching elements have to be made large enough to pass the required current. Energy is consumed from the supply to switch the large bank of transistors, and this energy is proportional to switcher update rate. A more complicated controller is therefore justified if it increases the number of small geometry devices while simultaneously reducing the number of switching rates at the large transistor banks.
With reference to FIG. 1a, there is illustrated an example output achieved for an exemplary input in a known PWM arrangement. FIG. 1a illustrates the input and output signals over two cycles, cycle 1 between time t0 and t1, and cycle 2 between time t1 and t2. The time instances t0, t1, t2 represent time instances at which there are successive rising edges of a clock signal. FIG. 1a illustrates a simple example in which the output voltage level can switch between one of two levels, V0 and V1. V0 may be a ground level, and V1 may be a positive voltage level. The input signal waveform is identified by reference number 1012. The output signal is identified by reference numeral 1002.
As illustrated in FIG. 1a, in the first cycle there is illustrated a rising ramp 1004, which rises from voltage V0 at time t0 to voltage V1 at time t1. Similarly in cycle 2 there is a rising ramp 1006 which raises from voltage V0 at time t1 to the voltage V1 at time t2. The output starts at voltage V1, and also starts each subsequent cycle at voltage V1.
With further reference to FIG. 1a, when the rising ramp signal 1004 crosses the falling input signal 1012, as denoted by reference numeral 1008, the output 1002 is transitioned to the voltage level V0. The output signal 1002 remains at voltage V0 until the end of the cycle at time t1, at which time the output is forced to voltage V1 for the start of the second cycle. In the second cycle when the rising ramp at 1006 crosses the falling input signal 1012, as indicated by reference numeral 1010, a transition to voltage V0 again occurs. The operation continues in this way.
As can be seen from FIG. 1a, the output signal 1002 is a poor representation of the input signal 1012. A problem in achieving an accurate representation of the original signal is that the PWM process can very accurately replicate the time instant of the falling edge of the waveform, but cannot replicate the rising edge of the waveform at all. The only way in which a rising edge can be carried forward is by setting the voltage to a fixed level, V1, at the beginning of each cycle.
With reference to FIG. 1b, it can be seen that when applying the conventional PWM technique to a multi-level buck converter, the accuracy for fast transitions degrades further.
With reference to FIG. 1b, there is again shown the input signal and output signal over a two cycle period from time t0 to time t2. In this multi-level example, the output signal can switch between one of five voltage levels: V0, V1, V2, V3, V4. The input signal waveform is denoted by reference numeral 2012, and the output signal is denoted by reference numeral 2002.
In this example, at the beginning of the first cycle the output voltage is at voltage level V1.
As shown in FIG. 1b, there is a ramp in each cycle for each of the voltage bands (five voltages providing four voltage bands). Thus in each cycle, for each band, the ramp starts at the lower voltage of the band, and terminates at the end of the cycle at the higher voltage of the band.
Immediately at the start of the cycle, a rising ramp 2011, being the ramp associated with the first band (between voltage levels V0 and V1) of the first cycle crosses the falling input signal 2012, and thus the output signal immediately transitions to voltage V0.
If the input signal is rising faster than the ramp, then quasi-linear PWM operation is not possible. This limit is reached when a slew rate of one full transition in (n−1) clock cycles, where n is the number of voltage levels. Therefore one full cycle of signal cannot be processed in less than pi*(n−1) clock cycles. For four voltage levels, the maximum bandwidth is one tenth of the clock rate.
At time t1 the voltage transitions to the highest voltage level V4 as this is the voltage level which most closely approximates the input signal waveform at that time. Thereafter the falling input signal 2012 crosses the rising ramp between voltage levels V3 and V4 of the second cycle at a given time, as denoted by reference numeral 2010, and at that time the output voltage is transitioned to the lower voltage level V3.
In a typical prior art PWM technique only a single transition is permitted in a given cycle, and thus once the transition from V4 to V3 takes place, the output signal remains at level V3 for the remainder of the cycle.
As can be seen from FIG. 1b, as there is no quasi-linear operation a substantial error is incurred.
The above described PWM technique incorporates the conventional method of obtaining PWM in which the ramp rises across the clock cycle, and the output signal is at an upper voltage level at the start of each cycle. This reproduces only falling edges.
The inverse to the conventional method for obtaining a PWM signal is that in which the ramp falls across the clock cycle, and the output waveform at the start of a cycle is set to the lower voltage level. This reproduces only rising edges.
It is an aim of the present invention to provide an improved switch mode voltage supply in which an accurate tracking of an input signal is provided.